As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area.
A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions, including what are commonly known as crown or cylindrical container stacked capacitors.
Many circuit designs require that capacitors make electrical connection with diffusion regions in bulk semiconductor (typically silicon) substrates. Some process flows for fabricating such circuits enable minimizing the spacing between adjacent devices by utilizing electrically conductive polysilicon plugs which project outwardly relative to the desired diffusion regions. Container capacitor constructions are then fabricated outwardly of the polysilicon plugs, with the electrically conductive storage nodes making ohmic electrical connection with the polysilicon plugs.
One such prior art construction is indicated generally in FIG. 1 with the numeral 10. Such comprises a bulk substrate 12, field oxide region 14 and a pair of word line construction 16, 18. A pair of diffusion regions 20 and 22 are provided adjacent word line 16. An insulating layer 24 is provided outwardly of word lines 16 and 18, and is provided with a pair of electrically conductive pillars or plugs 26 extending therethrough to the respective diffusion regions 20 and 22. An overlying layer 28 of borophosphosilicate glass (BPSG) is deposited, and includes a container opening 30 therethrough to conductive plug 26. A capacitor construction 32, including a storage node layer 34, a capacitor dielectric layer 36, and a cell polysilicon layer 38 are provided.
It would be desirable to improve upon such prior art capacitor constructions to result in increase capacitance.